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Chip Select CS_N in Uniphy ddr2 memory controller

Altera_Forum
Honored Contributor II
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Hello, 

 

I'm debugging a custom PCB: Cyclone V with UniPHY ddr2 IP controlling a single chip DDR2 memory. 

 

CS_N memory pin is pulled down but the signal is not routed to the FGPA. 

 

How does the UNIPHY controller use this signal? 

Is it mendatory, or can the controller still work fine without this signal driving the memory? 

 

Thanks.
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