Clamshell Top and Bottom Device

[Altera_Forum]

Hi There 

 Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits.  The address and bank address lines are shared between both devices in the clamshell, with the chip select signal used to selectively write to one device or the other or both.  The data bus is 16-bits wide (8 bits per device). But the control signals(ras, cas, we_n) for both the device have got different pin assignment. Does the controller need to generation 2 bit ras, cas,we.    I feel controller must generate only 1 bit cas, ras, we, but I dont understand why control signals have different pin assignment for both the device. Please respond    Regards Harsh Bandil

[Altera_Forum]

I didn't understand clearly from your post which pin assignment you're talking about. If the design is accessing two DDR2 bank with individual address and control lines, they must be operated by two individual controller instances. The Stratix II GX PCI Express Dev. Kit I know has a single bank with common address lines, however. Which board do you have? There are other Altera Dev. Kits with two individual DDR2 banks, but not Stratix II GX, as far as I know.

[Altera_Forum]

Thanks FVM, 

 I am using Altera CNIC 2a, which is based on StratixIIGX device, which has four independent banks of 256MB DDR-II. The DDR2 device on the board is MT47H128M8HQ-3:E (333MHz).   The address and bank address lines are shared between both devices in the clamshell, with the chip select signal used to selectively write to one device or the other or both.  The data bus is 16-bits wide (8 bits per device). But the control signals for both the device have got different pin assignments.  Since the memory is one, with 16 bit datapath, I doubt whether we really need to have two instances of controller. Suggest how to handle it.  Regards Harsh Bandil 

[Altera_Forum]

--- Quote Start ---  The address and bank address lines are shared between both devices in the clamshell, with the chip select signal used to selectively write to one device or the other or both. The data bus is 16-bits wide (8 bits per device). But the control signals for both the device have got different pin assignments.  --- Quote End ---   Sorry, I still don't understand. The control signals can be either shared, which to my opinion means, they connect to the same FPGA pin, each, or separate, connecting to different FPGA pins. In the latter case you need two controller instances.  By the way, I 'm unable to identify any "Altera CNIC 2a" board.

[Altera_Forum]

http://www.aliathon.com/c-nic_brief.pdf. Control signals are not shared between top and bottom device. Only address and bank signals are shared.

[Altera_Forum]

The datasheet is about a Xilinx dev kit, but is talking of independant DDR2 banks.  

 It may be the case, that the Altera version of the board, which apparently also exists, isn't compatible with present Altera DDR2 controller cores. You may need to contact the manufacturer regarding intended mode of operation and respective example designs for their boards.