FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Clarification on rx_st_empty Behavior for Unaligned Transfers (1 DWORD Length) in P-TILE :-

thanavignesh
新貢獻者 I
670 檢視

I have a few doubts regarding how the rx_st_empty signal is updated during unaligned transfers where the SOP and EOP are asserted in the same cycle, specifically for a length of 1 DWORD.

  1. For a write request with aligned address (e.g., address = 0), the valid data is located in rx_st_tdata[31:0], and the remaining bytes [255:32] are empty , leading to rx_st_empty = 7 (as only 1 DWORD is valid).
    What happens if the address is unaligned (e.g., address = 4)? The valid DWORD shifts to rx_st_tdata[63:32]. In this case:

    • Will rx_st_empty still update to 7 as before, considering the higher bits [255:64] and  [31 : 0] are invalid?
    • Or will it update to 6 since only [255:64] are empty?
  2. For other unaligned addresses (e.g., address = 8, C, 10, ..., 1C), where the valid DWORD keeps shifting to the right, how does rx_st_empty update in these cases Especially for .1 dword length case ?

  3. For a read request of 1 DWORD length, does rx_st_empty behave similarly to a write request with unaligned addresses, or is its value fixed regardless of alignment?

I’d appreciate any insights or examples to clarify how rx_st_empty behaves in such scenarios.

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3 回應
ventt
員工
552 檢視

Hi thanavignesh,


Thanks for reaching out.


Allow me some time to investigate your issue. I shall come back to you with the findings.


Thanks.

Best Regards,

Ven


ventt
員工
494 檢視

Hi thanavignesh,


My apology for the delayed response.


When the valid data is in rx_st_tdata[31:0] and the remaining data [255:32] is empty. The rx_st_empty_o will be 7 as the 7 dwords counted starting from the MSB are ignored.


The rx_st_tdata cannot be valid at rx_st_tdata[63:32] but not rx_st_tdata[31:0]. When the rx_st_empty_o is 6, the rx_st_tdata[63:0] should be valid. This applies for both read and write request.


The address alignment should be handled by user logic.


Thanks.

Best Regards,

Ven


ventt
員工
431 檢視

Hi thanavignesh,


As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.


After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.


Thanks.

Best Regards,

Ven


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