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Altera_Forum
Honored Contributor I
1,576 Views

Clock input port inclk[0] of PLL Error

Hi, I have the following Problem:  

 

Error (15065): Clock input port inclk[0] of PLL "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block 

Info (15024): Input port INCLK[0] of node "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|pll1" is not connected 

 

 

http://www1.minpic.de/bild_anzeigen_thumb.php?img=178419.jpg (http://www1.minpic.de/bild_anzeigen.php?id=178419&key=52065136&ende

 

I have no idea whats wrong because i´m still learning.I hope someone can help me.Maybe it´s an easy problem to solve.
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5 Replies
Altera_Forum
Honored Contributor I
119 Views

the Picture should show where the error is located?!

Altera_Forum
Honored Contributor I
119 Views

The error message is quite clear. What did you connecto to pll input port? 

On DE0 Nano it should be the 50MHz clock getting into fpga pin R8.
Altera_Forum
Honored Contributor I
119 Views

Yes i connect pin R8. I solved the problem but I was not a problem.In the SOPC Builder I checkd a button i should´t check.Thats all.Now everthing works fine. 

But thank you for your answer.
Altera_Forum
Honored Contributor I
119 Views

Hi DwiDz, 

please, could you say me what are you checked? 

 

Best Regards, 

Umberto
Altera_Forum
Honored Contributor I
119 Views

I solved this problem.  

Because you not connected Pin Label with symbol, in my project, PLL clk0 not connected with it's Pin Label