Hi, I have the following Problem:
Error (15065): Clock input port inclk[0] of PLL "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info (15024): Input port INCLK[0] of node "DE0_Nano_uCE0_Nano_uC_inst|clocks_0:the_clocks_0|altpll: DE_Clock_Generator_Audio|altpll_o152:auto_generated|pll1" is not connected http://www1.minpic.de/bild_anzeigen_thumb.php?img=178419.jpg (http://www1.minpic.de/bild_anzeigen.php?id=178419&key=52065136&ende) I have no idea whats wrong because i´m still learning.I hope someone can help me.Maybe it´s an easy problem to solve.Link Copied
the Picture should show where the error is located?!
The error message is quite clear. What did you connecto to pll input port?
On DE0 Nano it should be the 50MHz clock getting into fpga pin R8.Yes i connect pin R8. I solved the problem but I was not a problem.In the SOPC Builder I checkd a button i should´t check.Thats all.Now everthing works fine.
But thank you for your answer.Hi DwiDz,
please, could you say me what are you checked? Best Regards, UmbertoI solved this problem.
Because you not connected Pin Label with symbol, in my project, PLL clk0 not connected with it's Pin LabelFor more complete information about compiler optimizations, see our Optimization Notice.