Clocked Video Out VIP Timing analysis

[Altera_Forum]

Hello All,  

 I have been struggling for a few days now to solve my Timing analysis problems on my cyclone III design , but have had no luck at all.  I have simple design with a micron 8 mb sram controller, altera Test Generator, and Video , Altera Standard frame buffer ,Clocked out IP.  I have added, the VIP Video clocked out SDC Timing file to my time quest analyzer , as well as pll and sram contraints.  When Running Time quest and reading in the VIP Video clocked out SDC Timing file, I noticed that all the constraints in the Standard Altera VIP Video clocked out SDC Timing file(located altera\ip\clocked_out\lib),were ignored.  Further more when analyzing the system I notice that my design fails on Recovery paths on my PLL. After creating a report I have been able to figure out where the fail paths occur, but I have no idea how I can fix them.  -4.234 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.234 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.234 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.234 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.234 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.225 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.225 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.225 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.225 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7] inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0] -4.136 NiosTest_top:inst|NiosTest_top_reset_clk_0_domain_synch_module:NiosTest_top_reset_clk_0_domain_synch|data_out NiosTest_top:inst|alt_vip_itc_0:the_alt_vip_itc_0|alt_vip_itc_0_GN:auto_inst|alt_vip_IS2Vid:alt_vip_itc_0|alt_vip_common_fifo:input_fifo|dcfifo:input_fifo|dcfifo_9ii1:auto_generated|altsyncram_bi31:fifo_ram|ram_block5a0~portb_address_reg0 inst1|altpll_component|auto_generated|pll1|clk[0] inst2|altpll_component|auto_generated|pll1|clk[0]   I am attaching my project to this post, hope some one can help me.  Hope some one can help me. regards nadeem