So you must be using the standard DDR2 core and not the high performance DDR2 core. I believe you have to manually specify the phase for the resync clock.
The resync_clk is used as an interim capture clock between the DQS strobe and the mem_clk domain. The ideal phase depends on clock frequency as well as timing delays between the memory and FPGA. Ideally (providing maximum setup time between clock domains), it falls exactly at the midpoint between the DQS strobe and the 2nd mem_clk edge following the DQS strobe.
____ ____
DQS ----________| |____| |____|-----
^----^DQS latch
____ ____ ____ ____
resync_clk _| |____| |____| |____| |_
^resync latch
____ ____ ____ ____
mem_clk |____| |____| |____| |____
^mem_clk latch
Jake
