HiI designed a system with following flow: Clocked Video In (CVI) --------> Frame Buffer ------------> Clocked Video Out (CVO) Input video format is 1080p 60Hz. For frame buffer, I am using Tripple buffer with drop/repeat. System is working fine and I can see the output on the TV screen. However I have one confusion regarding the behavior of CVO. I expect the the output at CVO delayed by one frame time. I captured the signals as soon as CVO starts its first output (rising edge on DATA_VALID after seeing a falling edge on V_BLANK control bit) and looks to me it output a blank frame (video data = 24'h0). So I assume that when CVO is enabled by NIOS, it outputs a blank frame when it does not have any valid video frame coming from Frame Buffer and continues to do so as long as CVI is locking the input frame and FB has not buffered at least one full frame in the external memory. Please let me know if I am right in my assumption. Secondly, VPI guide states that CVI and CVO start their output at the frame boundary. What is the frame boundary (or start of frame) for CVI/CVO? Am I correct about my assumption of start of frame / frame boundary stated above, i.e. rising edge on DATA_VALID after seeing a falling edge on V_BLANK control bit. I am using 1080p 60Hz frame @ 148.5 MHz and video format is RGB 4:4:4 (24 bit). Regards Faisal
I don't know for sure, but I would guess the blank frame is generated by the frame buffer, not the CVO. You could try removing the frame buffer to see if you still get the blank frame. Connecting a test pattern generator straight to the CVO may also be an interesting experiment.
I am using MicroTronix's Multi-channel DDR2 controller with frame buffer. Its settings are bit different from Altera's one.For the frame buffer, I am using 1920x1080 input/output frame resolution, 8 bits per pixel and 3 parallel frames. The sync setting are default for DVI 1080pMy input video is at 148.5 MHz (1080p60) but I am using 160 MHz clock for all the Altera VIP cores to cater for delays in packet processing. I used a PLL on my Stratix-III FPGA to provide me 160MHZ VIP_CLK from reference clock of 50 MHZ. There is another PLL which generates clocks for the DDR2 memory, it is 267MHz. I have 64 DQ lines connected to DDR2, so for frame buffer I set 128 bit bus width, 512 entries pixel buffer and 128/256 burst size (both work ok). Also I am using tripple buffering, that is, enabled frame drop and repeat. I hope now you know all the settings that I am using for frame buffer.