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Valued Contributor III

Memory read issues with high performance DDR2 Conrollers

I am currently working on DDR2 High Performance Memory Controller. I am 

having read issues when we use High Performance Controller II. 

Note : Dint have any of the following issues when we were using just 

the High Performance Controller. 

In the simulation we do a memory write and a memory read @ the same address. During the write 

operation, we did write 88776655 and during the read you see the same 

value on the DQ bus(Read has taken place sucessfully). But on the user 

application data bus you see only 00005566(local_rdata). We are using the half rate memory controller and the clock fre is 320MHz. 


I have archived the project(cpu_subsys.qar). See the waveform file and check out these signals. 

mem_dq(during the read command)==88776655 






We use an half rate controller, check data signals dio_rdata3_1x, dio_rdata2_1x has all zeroz as though we are using a full rate controller. As data on dio_rdata3_1x n dio_rdata2_1x are zeros, you see the upper 16 bits for ctl_rdata and local_rdata are zeros. 

Please see the attachments. 

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