This has been bothering me for a while and I'm wondering if others have seen the same:In short, the output HS/VS from the clocked video output are not aligned. No matter what I do in the actual video chain when the CVO block reconstructs video it seems to have this problem.. According to various specs hs/vs need to be aligned exactly. That is what the standards call for and displays expect naturally. The offset isn't exactly even small, its some hundreds of pixel clocks apart in the way that VS goes up first and then HS follows later effectively cutting short the portch. Granted, it's not much in the grand scheme of things and will pass most lower end video analysators like QD780/MP500 but if I use something better like QD802 which actually seems to count pixel clocks then I get a big red failure. Again, most TV:s seem to lock and display picture just fine I just can't get approved compliance unless I tweak those pulses after the CVO. I run into this issue upon finding some brand new Sony television that did not lock to the signal. Once corrected after the CVO, the TV locked nicely. Anyone seen the same?
What is the exact board, or IP block you are using? It sounds like it's a bug in the IP, so I would make Altera or the IP provider aware of it.I've done video retimers in the past in an FPGA, and can tell you old CRT's are much more forgiving than most LCD flat panels. Pete