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SerialLite II simulation problem

Altera_Forum
Honored Contributor II
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Hello everyone: 

 

I have two test boards, each one has a Stratix IV FPGA. The project is to design a SERDES between these two boards. Currently, my work is to design SERDES in one FPGA and to test whether it works well. I use SerialLite II and Altgx_reconfig Megafunction to implement SERDES. SerialLite II core is configured in streaming mode, 8xlane @ 3.125 Gb/s. 

 

The design is written in VHDL language. The cores are generated by Quartus II 10.1 and I use Modelsim-altera starter edition 6.6d to simulate my design. I wrote a testbench in which the rxin port of SerialLite II core is directly connected to txout port and I expect the data from rxrdp_dat port is the same as the data I send into txrdp_dat port. 

 

Now the problem is after simulation I found the value of txrdp_dav port is always "0", which means the input FIFO buffer is always full. So the SerialLite II core can not receive any data. Does anyone konw what may cacuse this problem? 

 

Thank you very much. 

 

Xuming
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