FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

Color Space Converter not generated corectly

Altera_Forum
Honored Contributor II
814 Views

Hi all, I try to use the CSC IP for converting my Video Stream from RGB to YCrCb. It use the MegaWizard to generate a CSC VHDL IP Module suiting my needs. But the generated file csc.vhd has a syntax error. This is very strange, but not the real problem. when I start the synthesis following errors happen.  

Info (12128): Elaborating entity "csc_in" for hierarchy "csc_in:sRGB_YCrCb_1" Warning (277001): IP Generator Warning: This module has no ports or interfaces Info (12021): Found 2 design units, including 1 entities, in source file db/csc_in_gn.vhd Info (12022): Found design unit 1: csc_in_GN-rtl Info (12023): Found entity 1: csc_in_GN Info (12128): Elaborating entity "csc_in_GN" for hierarchy "csc_in:sRGB_YCrCb_1|csc_in_GN:auto_inst" Warning (12158): Entity "csc_in_GN" contains only dangling pins .... Error (12002): Port "clock" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_data" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_ready" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_valid" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_data" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_ready" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_valid" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "reset" does not exist in macrofunction "sRGB_YCrCb_1"  

 

They are correct, because the "db/csc_in_gn.vhd" file has a entity with no ports, but why? 

Did someone have the same problem? I use Quartus 13.1 with update 2 installed and a Cyclone 5 SoC. ( The error also happened before the update) 

 

Regards, 

Chris
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
90 Views

 

--- Quote Start ---  

Hi all, I try to use the CSC IP for converting my Video Stream from RGB to YCrCb. It use the MegaWizard to generate a CSC VHDL IP Module suiting my needs. But the generated file csc.vhd has a syntax error. This is very strange, but not the real problem. when I start the synthesis following errors happen.  

Info (12128): Elaborating entity "csc_in" for hierarchy "csc_in:sRGB_YCrCb_1" Warning (277001): IP Generator Warning: This module has no ports or interfaces Info (12021): Found 2 design units, including 1 entities, in source file db/csc_in_gn.vhd Info (12022): Found design unit 1: csc_in_GN-rtl Info (12023): Found entity 1: csc_in_GN Info (12128): Elaborating entity "csc_in_GN" for hierarchy "csc_in:sRGB_YCrCb_1|csc_in_GN:auto_inst" Warning (12158): Entity "csc_in_GN" contains only dangling pins .... Error (12002): Port "clock" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_data" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_ready" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "din_valid" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_data" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_endofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_ready" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_startofpacket" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "dout_valid" does not exist in macrofunction "sRGB_YCrCb_1" Error (12002): Port "reset" does not exist in macrofunction "sRGB_YCrCb_1"  

 

They are correct, because the "db/csc_in_gn.vhd" file has a entity with no ports, but why? 

Did someone have the same problem? I use Quartus 13.1 with update 2 installed and a Cyclone 5 SoC. ( The error also happened before the update) 

 

Regards, 

Chris 

--- Quote End ---  

 

 

I have a similar issue with an intelacer instance on an Arria V device. 

 

Have you recieved an answer ?
Reply