FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6529 Discussions

Combine DSP Builder and Quartus II Project

Altera_Forum
Honored Contributor II
1,413 Views

Hi! 

 

I wanted to ask, if it is possible, to combine a DSP Builder Project with a Quartus II Project. 

 

I know how to compile a DSP Builder Project in Quartus II.  

 

For my case, I would like to create a Project, where I can implement basic Signal Operation (e.g. clock recovery) in Quartus and more complex Operation (RS encoding, modulation) in DSP Builder. 

 

Is it then possible to combine those Project?  

Like one is then a Black Box in the other? 

 

I am grateful for any hints and help.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
686 Views

You can just add the .mdl file to the Quartus project. Assuming you've previously generated from the mdl file (so that you have .mdlxml file next to it), then the remaining HDL files should then be generated during Analysis and Synthesis.

0 Kudos
Altera_Forum
Honored Contributor II
686 Views

Thank you for you answer! 

 

I included a small self made and compiled dsp builder project in an empty quartus II project. I used the tcl command line and executed the "source <file directory>/*_add.tcl" file, which was generated from simulink. 

 

Then I had, as you mentioned, the *.mdl and *.mdlxml files in my quartus Project. I compiled it and afterwards I saw all the vhd files in the Hierarchy. But in the File Window there were only the mdl and mdlxml files.  

 

Do I have to import the generated vhd files from the <project>/db directory manualy then? Do I have to create symbols then for each vhd file? 

 

In the end I would like to have a schematic as top level entity file where i can integrate the dsp builder project (or parts of the project) as black box. 

 

I think I still make a mistake somewhere.
0 Kudos
Altera_Forum
Honored Contributor II
686 Views

If you want the vhdl to be in your project, you should consider using HDL Export as described in http://www.alteraforum.com/forum/showthread.php?t=5550 (http://www.alteraforum.com/forum/showthread.php?t=5550)

0 Kudos
Altera_Forum
Honored Contributor II
686 Views

Thank you! 

 

I think this could work. I used the HDL Export in the DSP Builder and afterwards I added the <project_name>.qip File to my empty quartus II Project. 

 

I then created a symbol from the vhd File <dsp_project_name>_GN.vhd. 

(This should be the right file. What does this GN mean?) 

 

Finally I got a Symbol (Black Box) with all the inputs and outputs I created in the DSP Project. Do I need to do pin assignment for the in- and outputs then in the DSP Builder project?
0 Kudos
Altera_Forum
Honored Contributor II
686 Views

DSP Builder doesn't automatically create Pin Assignments unless you add a Pin Assignment blocks or add a Virtual Pins block. If you have done those, they will be created into the output directory when DSP Builder is generating. 

 

I don't think they can be added to a qip file, so you would have to manually invoke the pin assignments script generated by DSP Builder. I haven't tried this so you'd have to experiment.
0 Kudos
Reply