Comparison between DDR2 controller and high performance controller

[Altera_Forum]

I would appreciate if someone can explain the feature difference between the two IPs or point me to a resource for same. I am referring to the ones described in here: 

http://www.altera.com/literature/ug/ug_ddr_sdram.pdf and here: http://www.altera.com/literature/hb/external-memory/emi_ddr_ug.pdf   Thanks, Piyush

[Altera_Forum]

What's your intended target hardware? Besides Stratix II/II GX no FPGA family is supported by both IPs. So you most likely don't have a choice at all. 

 Generally, the DDR2HP core is involving a higher level interface with more data buffering and width/speed translation, as required by a typical application.

[Altera_Forum]

FvM, Thanks for the prompt response. I am targeting a Stratix II GX device and currently have a working model of the DDR2 Controller (250 MHz, 64-bit data bus), which is based on an older version (7.1) of Altera's reference design. I suspect that it is using only half the data bandwidth since local bus, though 128-bit wide, carries 2 64-bit duplicate values. My application needs to squeeze out as much storage and performance as possible. I am happy with speed performance so far, but I wonder if non-HP design is restricting me to only half the storage (256 MB SDRAM providing only 128 MB capacity).

[Altera_Forum]

--- Quote Start ---  I wonder if non-HP design is restricting me to only half the storage  --- Quote End ---  Perhaps, if configured incorrectly? But I only used the HP controller with Arria yet.

[Altera_Forum]

The regular DDR2 controller does not restrict you to half the storage (that would be a pretty useless controller). The main difference between the old DDR2 controller and the HP controller is the introduction of the altmemphy megafunction in the newer controller. You no longer need the feedback clock in the newer controller. Also, with the new HP controller, I believe they have made some efficiency improvements in the control path. 

 Jake

[Altera_Forum]

First of all, apologies for delayed response. I have again carefully gone through Altera's reference designs (DDR2 for Arria II) and as far as I can tell, only 50% of SDRAM's capacity is utilized due to mismatch between DDR2 local bus size (128-bits) and PCIe data bus size (64-bits). To be precise: 

 1. DDR2 controller's 'local_rdata' port is mapped to 128-bit 'TxReadData' signal 2. Tx_Top's 'TxReadData_i' is mapped to 'TxReadData[63:0]' which means that higher-order 64-bits of TxReadData are essentially discarded in this design.  I had also thought of reprogramming the DDR2 controller to 64-bit local bus width (i.e. 32-bit internal data bus) but that automatically reduces the memory size by 50% (as seen in Mega Wizard).  Has anyone run into these issues and what would be the easiest way to bypass this restriction? If anyone has tried, could you please let me know how much of an effort it would be to modify Tx_Top app logic to transmit 128-bit data over 64-bit bus?  Thanks, Piyush

[Altera_Forum]

Well you just added a whole new dynamic to the issue. Your problem is not the DDR2 controller but in fact the way the PCIe IP is connected to the controller. Yes it is true that if you only connect half of the read or write data bus you will in fact only be using half of the memory. 

 Jake