Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
736 Views

DDR2 SOPC example on Stratix IV issue

Hi, 

 

I am trying to run the walkthrough example on EMI_TUT_DDR-1.0 in the following tutorial which is done on a Cyclone FPGA. 

I follow the steps and my sopc_top generates a top level which has some extra pins like oct_ctl_rs_value_to_the almemddr[13..0] and oct_ctl_rt_value_to_the almemddr[13..0] and some aux outputs. I read somewhere that I need to use a cal_oct core and connect those oct_ctl signals to that core. Now I don't know wheere I should connect s2pload, calibration_request, calibration_busy and Cal_shirt_busy and clock signals. When I compile (after the pin allocation), I get the following errors.  

Error: I/Os have a memory interface specific sub-block, but have no memory interface grouping assignment specified 

Is there any tutorial done on Stratix 4 which explains how to do it? Any help is much appreciated. I feel Altera's tutorials are not comprehensive.
0 Kudos