Compile DSP Builder 9.0 IP in QII 9.1SP2

[Altera_Forum]

Hi there, 

 We are using QII 9.1SP2 for our projects but we have an IP created using DSP Builder 9.0 with Matlab 2007. Because Matlab 2007 doesn't work with DSP Builder 9.1, we can't really regenerate the IP for QII 9.1 (unless we update our licenses).  Is it possible to directly plug the VHDL files generated from DSP Builder 9.0 into our project and compile under QII 9.1SP2?  I tried it and it gives me the following error:  Error: IP Generator Error: The file xxxx.mdlxml in the directory xxxx can not be read. It may be corrupted.(The following exception occured while validating field: _clockdomainList of class: com.altera.dspbuilder.mdlxml.component_gen.Model: The field '_resetLatency' (whose xml name is 'ResetLatency') is a required field of class 'com.altera.dspbuilder.mdlxml.component_gen.Clockdomain)  I know Altera provides a way to update the IPs from older version of megawizard, but do they also have a way to update the IPs from older versions of DSP builder? After all, all the information the DSP builder needed to generate the IP are already there.  Thanks, Hua

[Altera_Forum]

i suggest opening the QII project created by Signal Compiler in Quartus II 9.0, and exporting the Top level partition as a .qxp. then add the .qxp to your QII 9.1sp2 project and instantiate as normal

[Altera_Forum]

Thanks, thepancake. Does that mean Altera doesn't have a direct update solution?

[Altera_Forum]

i think its going to get tricky because QII has new IP libraries but the older DSP Builder can't really pull them in or just swap out the old IP for the new one. maybe its possible, but probably not worth the trouble 

 i'm partial to the single file .qxp flow :)

[Altera_Forum]

It's possible you could also manually fix the mdlxml file. 

 You should find some elements in that file like <clockdomain name="..." ... />. Try adding a new attribute resetLatency="0" like this:  <clockdomain name="..." resetLatency="0" ... />