FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5875 Discussions

Compiling Encrypted Design Files

Altera_Forum
Honored Contributor I
943 Views

I'm attempting to compile the Megacore Triple Speed Ethernet module for sumulation using Active HDL. I want to compile the library files into a resource library and attach that to my simulation. However, the sources are encrypted, and the tool bombs out. How do you all handle that issue? I've been searching for a couple days. I'm also in communication with Aldec about this, but progress has been slow. I can't believe I can't find a published solution:evil: 

 

Thanks in advance.
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
78 Views

Did you notice the eda tab in the MegaWizard for TSE? It's about your problem.

Altera_Forum
Honored Contributor I
78 Views

Hi, thanks for your response. I tried the EDA tab, but got this message: 

 

 

--- Quote Start ---  

 

Error: Ethernet HDL generation failed. 

Info: ethernet: IP Functional simulation Model Creation Failed. The following error was returned. 

 

--- Quote End ---  

 

I guess I don't have the required simulation libraries.
Altera_Forum
Honored Contributor I
78 Views

O.K., possibly something is missing. However, there's no other way for functional simulation of the encrypted cores than using the special simulation libraries. I don't use TSE and don't know about possible general issues, but it works well with other cores.

Altera_Forum
Honored Contributor I
78 Views

Thanks again. Something is definitely missing. I'm researching it now. I'll upudate when I have a solution.

Reply