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Altera_Forum
Honored Contributor I
1,485 Views

Configuring triple speed ethernet MAC with National DP83640 PHY in MII interface

I have made my own custom Cyclone IV Nios board with two DP8360 PHY. I also used the TSE MAC from Altera. 

 

I'm trying to test this board using the simple socket application. 

 

First I've updated the altera_avalon_tse.c file: 

 

alt_tse_phy_profile DP83640 = {"National DP83640", /* National DP83640 */ 

DP83640_OUI, /* OUI */ 

DP83640_MODEL, /* Vender Model Number */ 

DP83640_REV, /* Model Revision Number */ 

0, /* Location of Status Register (ignored) */ 

0, /* Location of Speed Status (ignored) */ 

0, /* Location of Duplex Status (ignored) */ 

0, /* Location of Link Status (ignored) */ 

0, /* No function pointer configure National DP83640 */ 

&DP83640_link_status_read /* Function pointer to read from PHY specific status register */  

}; 

 

/* add supported PHY to profile */  

alt_tse_phy_add_profile(&MV88E1111); 

alt_tse_phy_add_profile(&MV88E1145); 

alt_tse_phy_add_profile(&DP83865); 

alt_tse_phy_add_profile(&DP83848C); 

alt_tse_phy_add_profile(&DP83640); 

 

 

 

/* @Function Description: Read link status from PHY specific status register of DP83640 

* @API Type: Internal 

* @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group 

*/ 

alt_u32 DP83640_link_status_read(np_tse_mac *pmac) { 

alt_u32 link_status = 0; 

alt_u32 reg_status = IORD(&pmac->mdio1.reg10, 0); 

 

/* If speed == 10 Mbps */ 

if(reg_status & 0x2) { 

link_status |= 0x8; 

/* Else speed = 100 Mbps */ 

else { 

link_status |= 0x4; 

 

/* If duplex == Full */ 

if(reg_status & 0x4) { 

link_status |= 0x1; 

 

return link_status; 

 

 

 

 

Then I've updated the altera_avalon_tse.h file: 

 

 

/* National 10/100 PHY on PHYWORKX board */ 

enum { 

DP83640_OUI = 0x080017, 

DP83640_MODEL = 0x0E, 

DP83640_REV = 0x01 

}; 

 

 

/* @Function Description: Read link status from PHY specific status register of DP83640 

* @API Type: Internal 

* @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group 

*/ 

alt_u32 DP83640_link_status_read(np_tse_mac *pmac); 

 

 

 

 

 

After compiling and executing the program, I get the following output: 

 

nios2-terminal: connected to hardware target using JTAG UART on cable 

nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) 

 

InterNiche Portable TCP/IP, v3.1  

 

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  

prep_tse_mac 0 

Your Ethernet MAC address is 00:07:ed:ff:cd:15 

prepped 1 interface, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x08000400 

INFO : PHY National DP83640 found at PHY address 0x01 of MAC Group[0] 

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

INFO : PHY[0.0] - Checking link... 

INFO : PHY[0.0] - Link established 

INFO : PHY[0.0] - Speed = 100, Duplex = Full 

OK, x=0, CMD_CONFIG=0x01000000 

 

MAC post-initialization: CMD_CONFIG=0x05000203 

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created 

mctest init called 

IP address of et1 : 0.0.0.0 

Created "Inet main" task (Prio: 2) 

Created "clock tick" task (Prio: 3) 

 

And it get stucked here. 

 

 

 

As you can see the DHCP is not working (IP address of et1: 0.0.0.0). Detail: The same configuration works fine for Terasic DE-115 board (cyclone iv + marvell 88E1111).  

 

Am I missing anything? 

 

Best Regards,
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5 Replies
Altera_Forum
Honored Contributor I
43 Views

Are you sure the PHY chip is actually working? You can add some Signaltap probes to the interface between the TSE mac and the PHY chip to see if packets are coming and going. 

Are you sure the DP83640 is using the same specific register as the DP83848C? I find it odd that this function doesn't actually check the link status... it just assumes that the link is established at 100MBps if the PHY doesn't report 10Mbps. To be thorough, it would require an additional step here.
Altera_Forum
Honored Contributor I
43 Views

Dear Daixiwen, 

 

Thanks for the reply. I've added signaltap probes and I can see that data is coming from phy to the mac. I've used rxclk and trigger on rxdv. When I disconnect the ethernet cable, the phy stops sending date. 

For another hand, the mac is not sending any data to the phy. It looks like it is ignoring the data received. 

 

Best Regards, 

 

Celso
Altera_Forum
Honored Contributor I
43 Views

Well it's a good sign. No either the frame sent by the phy isn't valid, for one reason or the other, or something causes the software not to answer the packets. 

The TSE can optionally include statistic counters. You need to enable them in SOPC builder IIRC, and then you can read those registers (see table 5.4 of the user guide (http://www.altera.com/literature/ug/ug_ethernet.pdf)). It should tell you if the TSE core detected valid or invalid packets.
Altera_Forum
Honored Contributor I
43 Views

Problem solved !!! 

 

I've compiled the design using Quartus 11.0 and the simple socket server worked. 

 

Daixiwen, thanks for your help. 

 

Celso
Altera_Forum
Honored Contributor I
43 Views

hii.. 

can any one please let me know how to configure the registers of dp83640..? is it to be done through some software or anything else.. am new to this.. please an earliest reply is expected.. its urgent..
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