I am using the DDR2 SDRAM Controller generated by Megawizard of Quartus9.1.The basic reading and writing request can successfully processed by controller, but, when the reading request is encountered with the auto-refreshing operation, the controller can not processed this read request! There is one cycle uncertain state, "x", after the refresh operation. However, the write request can be bufferred and processed after a auto-refreshing operation. Pictures attached illustrate the confliction between read request and auto-refresh, and the right processing of write requests. By the way, the device I am using is Stratix II, and the DDR model in the simulation is downloaded from mircon. Background: DDR auto-refresh in every 7.8 us.
If you are using the HPCII then the controller has a command fifo 8 commands deep. If the memory is busy refreshing then this fifo may get full and the controller will deassert local_ready at which time you cant issue any further commands.I've never seen the X after refresh is finished however??
Actually, I am using the DDR2 SDRAM Controller 9.1 rather than high performance controller. As I know from the "supports", the commands fifo depth is 3 for this kind of Controller. Once the FIFO is full, the local_ready signal will be deasserted.However, in the case I encountered with, the ready was never deasserted and there is one cycle of X. After that, the Controller did not response to read and write request any more. Is there other operations that may cause this problem?
9.1 should still be the high performance controller. I've never seen a simulation present a X mid way through.I would try the example top design with the example driver and see if that simulates ok.