FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6062 Discussions

Consolidate bugs of PCIe examples

Altera_Forum
Honored Contributor II
895 Views

Hi,  

I'm playing around with PCIe on Arria II.  

As you know, in order to use PCIe, you need a lot of "supporting" logics, such as computing the available credit, arbitration between multiple DMA/Tx/Completor ... etc .. However, Altera doesn't have a "formal" release for these ware and I've been digging on the Example provided whenever the PCIe core is instantiate.  

 

So, my guess is that this "reference design" is not BUG-FREE. Hopefully, the mass community can update bugs so that this core is stable enough.  

 

So far, I found 1 bug:  

 

--- Quote Start ---  

 

- in the file altpcierd_rxtx_downstream_intf.v:  

- the logic that controls the mem_wr_ena signal, 

if(rx_start_write==1'b1) begin .... 

 

else if(rx_dv==1'b1)  

mem_wr_ena <= 1'b1; 

mem_wr_addr <= mem_wr_addr+1; 

else  

... 

 

------ 

The error happens when you poll one of the registers while DMA is running.  

it condition should be (rx_dv = 1'b1 && cstate_rx= RX_DV_PAYLD) 

...  

without condition of cstate_rx, the register is accidentally written by rx_dv which is asserted during some other transactions,  

 

--- Quote End ---  

0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
113 Views

Another bug,  

 

 

--- Quote Start ---  

 

- in the file altpcierd_rxtx_downstream_intf.v 

- the logic that controls the signal tx_busy 

tx_busy is asserted too late.  

It is asserted on the 2nd cycle after arbitration is granted and data is valid for transmission. 

The error occurs when the PCIe tx_stream_ready is de-asserted right in the middle cycle after ARBITRATION is granted and TX_BUSY is asserted, the whole state machine gets stuck. 

See picture,  

the tx_sel_pcnt is the abitration grant signal, it is deasserted right after the statemachine sees that it is granted access. The state-machine is stuck there wait for acknowledgement from the PCIe core.  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=3177&stc=1&d=1287051603  

 

 

--- Quote End ---  

Altera_Forum
Honored Contributor II
113 Views

FYI, i believe that all DMA Tx engines in the example should assert tx_busy 1 clock earlier to claim the bus access.

Altera_Forum
Honored Contributor II
113 Views

the PCIe system is now quite stable and can stream data to PC at the datarate of ~10.5Gb/s. :).

Altera_Forum
Honored Contributor II
113 Views

Thank you very much for share it. 

I'm starting now to implement PCIe on StratixIV and know in advance some bugs will make me loose less time.
Altera_Forum
Honored Contributor II
113 Views

• chaining_dma: search for »-- todo …«, e.g. in altpcierd_cpld_rx_buffer.vhd 

 

• chaining_dma: complete lack of completion timeout mechanism (for DMA read requests).
Altera_Forum
Honored Contributor II
113 Views

Has anyone achieved more throughput for the PCIe x8 gen2 reference design? 

Theoretically, it is possible to run at 5Gb/s x 8 = 40 Gb/s. Am I correct? 

We can stream to PC at about 13Gb/s right now.
Altera_Forum
Honored Contributor II
113 Views

Is there an Errata list on Chaining DMA PCIe Reference Design?

Altera_Forum
Honored Contributor II
113 Views

Is it true, that all Altera PCIe reference designs ( AN456 and AN431 ) only transmits TLP packets for bandwidth measurement, and therefore are not practical reference designs for streaming applications?

Reply