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Converting FPGA design to VLSI design

Altera_Forum
Honored Contributor II
1,005 Views

I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement. However, I use some IP Cores in the original design including FFT, multipliers. Can I synthesize and route the IP Cores with RTL compiler and SOC Encounter, respectively? Does anyone know the step? 

 

 

Thanks!
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5 Replies
Altera_Forum
Honored Contributor II
100 Views

Multipliers should be available with cadence, for FFT you need to look for an alternative IP or design it yourself. Altera FFT is protected IP and can't be used with other tools for synthesis.

Altera_Forum
Honored Contributor II
100 Views

Thanks for your reply

Altera_Forum
Honored Contributor II
100 Views

Hi, 

just to mention.. If the intention is to transfer the FPGA to an ASIC, maybe it's worth having a look at the hardcopy option offered by ALTERA...
Altera_Forum
Honored Contributor II
100 Views

 

--- Quote Start ---  

Hi, 

just to mention.. If the intention is to transfer the FPGA to an ASIC, maybe it's worth having a look at the hardcopy option offered by ALTERA... 

--- Quote End ---  

 

 

Thanks for your reply. How can I get the hardcopy?
Altera_Forum
Honored Contributor II
100 Views

Hi, 

just get started at altera.com with selecting Hardcopy devices.... 

 

http://www.altera.com/devices/asic/hardcopy-asics/about/hrd-index.html 

 

Regards ;-)
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