PCIe Hard IP MSI Interrupt handling

[Altera_Forum]

I am using PCIe Hard IP in my QSys based system implemented in Startix IV. On the software side, we use Jungo driver. I need to know a bit more about how the MSI interrupts work. I went through the PCIe userguide, but I could not get an understanding how to use the multiple MSI messages (is that possible in Qsys based design?) and how to pass the message, so that the Software can know the source of the interrupt (pass the Interrupt Vector as the MSI message). There is a Message Address in MSI Capability Structure which I assume is the System Memory Address where the message will be written by the Hardware? And what about the 'Message Data'? What is the use for that? What is the use for multiple MSI packets?

[Altera_Forum]

--- Quote Start ---  I am using PCIe Hard IP in my QSys based system implemented in Startix IV. On the software side, we use Jungo driver. I need to know a bit more about how the MSI interrupts work. I went through the PCIe userguide, but I could not get an understanding how to use the multiple MSI messages (is that possible in Qsys based design?) and how to pass the message, so that the Software can know the source of the interrupt (pass the Interrupt Vector as the MSI message). There is a Message Address in MSI Capability Structure which I assume is the System Memory Address where the message will be written by the Hardware? And what about the 'Message Data'? What is the use for that? What is the use for multiple MSI packets?  --- Quote End ---   It's from MSI-X table in you BAR. This table consist address and data. Send data to address for interrupt.

[Altera_Forum]

I am not talking about MSI-X, but the simple MSI. So the driver would configure the MSI capability structure at Config Space Address 0x050 ..0x5C.  

0x050 Message Control, Configuration MSI Control Status Register Field Descriptions, Next Cap Ptr, Capability ID 0x054 Message Address 0x058 Message Upper Address 0x05C Message Data  So, in QSys you have multiple devices connected which can interrupt the PCIe endpoint core (upto 16). My requirement is - Know the source of the interrupt (which device triggered it) without going to go back and read the interrupt status register (CRA - 0x40) - Pass specific data along with MSI packet as the message. Is that possible? - What is the purpose of Message Data (in Config Space 0x5C) ? Is that something you can use to pass specific data from the endpoint core by the individual device? - The Message Address (0x54 ) is the system memory address where it would write the data specified in 0x5c?

[Altera_Forum]

I have read the PCIe user guide and I found that the signal app_msi_req produces the interrupts to pci express.  

 Also I check the followed registers that are responsible for generating msi interrupts:   1. Set the MSI Enable at bit[0] of MSI Control Status register, this bit is mapped to bit[16] of configuration space register offset 0x50.  2. Set the Interrupt Disable at bit[10] of Command Register at configuration space offset register 0x4 to disable legacy interrupt.  3. Set the Bus Master at bit[2] of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.  Every 1 sec I enable the app_msi_req inorder to see every 1 sec interrupts in my driver. app _msi_tc and app_msi_num assigned to zero. Still I can not see interrupts in my driver. The interrupt handler is not called.     I would like to ask: 1) What should I check more? Do I miss something important?  2) How can I simulate this desing to check if I get app_msi_ack=1 ??  3) Should I change more signals?  Thanks in Advance!

[Altera_Forum]

Hi tonisss, 

 I am having similar problems with enabling the MSI interrupts. Done steps 1 to 3, but how to enable the app_msi_req? Writing which register enables this bit?  Thanks