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Good Day everyone!
I have a troubles in understanding how to create a megacore DDR3 which must be based on ARRIAIIGX family's IC! I plan to use a memory like MT41J64M16JT-15E (2*x16bits) & EP2AGX65DF25C5 FPGA. I'm sure that is this forum have someone who can help & explain how to create without a mistakes "step-by-step":) Best Regards, Roman.Link Copied
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So there are no examples for Arria II GX board? These are the best references.
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Thanks for the answer, Dear Socrates!
Yes of course, Altera has the best on-line tranings & I like that! But most of examples based on UniPhy ... I must use the ALTMEMPHY! Besides the traning http://www.altera.com/education/training/courses/omem1110 based on UniPhy & therefore there are not so full-valued for me! Also I would be glad if you explain me how to place x32 DDR3 on the 3A,4A or 7A, 8A banks of EP2AGX65DF25C5? I tried to create the same project like this, but unfortunately I got a mistakes, I supose that I'm doing something wrong ... Best Regards, Roman.- Mark as New
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DDR, DDR2 and DDR3 memory devices has to be interfaced to special (dedicated) FPGA pins. Run Pin Planner and enable showing of DQ/DQS groups - You'll see which pins can be used as data pins, which pins must be DQS, etc... Also some banks are capable of faster rates, some are not, but I am not sure about Arria II, since I use Cyclone III.

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