Custom Avalon-MM salve IP

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Dear all 

I have an IS61WV25616BLL device on board and want to add a custom Avalon-MM salve IP to be able to use the ram. Here is my custom verilog code.but when I run the small memory test. It fails can you suggest me what is the problem. // sram_controller.v // This file was auto-generated as a prototype implementation of a module // created in component editor. It ties off all outputs to ground and // ignores all inputs. It needs to be edited to make it do something // useful. //  // This file will not be automatically regenerated. You should check it in // to your version control system if you want to keep it. module sram ( //avalon data bus input wire clk, // clock.clk input wire [17:0] avs_s0_address, // s0.address input wire avs_s0_read_n, // .read_n output wire [15:0] avs_s0_readdata, // .readdata input wire avs_s0_write_n, // .write_n input wire [15:0] avs_s0_writedata, // .writedata input wire avs_s0_chipselect_n, // .chipselect_n input wire [1:0] avs_s0_byteenable_n, // .byteenable_n //sram data bus inout wire [15:0] sram_data, // sram_data.export output wire [17:0] sram_address, // sram_address.export output wire sram_ncs, // sram_ncs.export output wire sram_nwe, // sram_nwe.export output wire sram_noe, // sram_noe.export output wire [1:0] sram_byteenable_n // sram_byteenable_n.export );  assign sram_data = avs_s0_write_n ? avs_s0_writedata : 16'bz; assign avs_s0_readdata = sram_data; assign sram_address = avs_s0_address; assign sram_ncs = avs_s0_chipselect_n; assign sram_nwe = avs_s0_write_n; assign sram_noe = avs_s0_read_n; assign sram_byteenable_n = avs_s0_byteenable_n; // TODO: Auto-generated HDL template endmodule