- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello dlim,
I modified the custom Dipalyport Receiver board. The Modified point is CLKUSR pin only
DisplayPort Receiver function still doesn't work.
I attached two picture.
Picture 1 : cyclone 10gx transceiver PHY user Guide (20.1) page 259
Picture 1: I probing from my board.
In my system, the rx_is_lockedtodata signal and rx_is_lockedtoref are always low (it is problem)
Can you advice how to make it to work ?
My concern is rx_cal_busy and rx_analogreset signal is overlapping (?)
I didn't change anything in bitec-reconfig_alt_c10.v and xcve_reconfig_arbiter.sv.
I checked all reconfiguration signals. it works good.
the calibration step works good because rx_analogreset asserted.
I think the PLL(rx_cdr_refclk0 : 135MHz) doesn't lock.
Michael
Link Copied
- « Previous
-
- 1
- 2
- Next »
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
I am doing DisplayPort comparability test.
I found Desktop PC included Video card detect right resolution but the some laptop PC doesn't output video signal due to detect wrong resolution. My DP core is non GUP mode so I can't find the problem. I guess the reason of trouble is in DP Link training sequence.
Can you recommend how to solve the problem ?
Thank you
Michael
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Michael,
You are welcome !
FYI... Intel support structure is on a case by case basic.
For now, I am setting this case to closure but feel free to post new forum thread if you still have new enquiry in future.
Thanks.
Regards,
dlim
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page
- « Previous
-
- 1
- 2
- Next »