I modified the custom Dipalyport Receiver board. The Modified point is CLKUSR pin only
DisplayPort Receiver function still doesn't work.
I attached two picture.
Picture 1 : cyclone 10gx transceiver PHY user Guide (20.1) page 259
Picture 1: I probing from my board.
In my system, the rx_is_lockedtodata signal and rx_is_lockedtoref are always low (it is problem)
Can you advice how to make it to work ?
My concern is rx_cal_busy and rx_analogreset signal is overlapping (?)
I didn't change anything in bitec-reconfig_alt_c10.v and xcve_reconfig_arbiter.sv.
I checked all reconfiguration signals. it works good.
the calibration step works good because rx_analogreset asserted.
I think the PLL(rx_cdr_refclk0 : 135MHz) doesn't lock.
I attached two picture, it is for previous mail.
I captured all reconfiguration interface address and data. It looks correct.
The read and write operation repeated each channel but I captured only one channel.
I think the CDR pll doesn't lock. I checked 135MHZ clock. it is ok
ok, looks like transceiver calibration can be completed and it's not stuck in reset mode anymore
I have 2 suggestion for you. You should isolate whether the CDR loose lock issue is caused by your board issue or your Quartus design issue.
To rule out potential board issue :
To rule out potential Quartus design issue
I installed C10GX_toolkit_demo design kit and I got same result as mine.
I probed internal signal as below
pll_locked : always "L" : means doesn't locked
locked : always " L" : this signal is IOPLL lock signal for test. but the 16MHZ clock comes out
rx_is_lockedtodata : always "L" : same result as my design
I attached C10GX_toolkit_demo design and Board schematic (power portion)
I think my board has a problem in PLL function and Power connection is correct or not (?)
Can you review where is wrong connection ?
I am not power expert but I do noticed 2 main concern that alert me.
It's very dangerous if there is still issue with your board design. I strongly recommend you to perform full board schematic review again. Below is one good reference doc that can help you on board schematic review
RREF pin should be 2K Resistor.
You mean the VREFB (Input reference voltage) need to connect GND because I didn't use DDR3 and I use LVDS TX only (No need VREF voltage).
Can you explain more information for very dangerous issue ?
Does it mean the chip goes to HOT ?
(FPGA consumed total current is Max less 300mA, I think it is not much but I added the heatsink).
By dangerous I mean if your board design connection is not done correctly then it may impact your FPGA design functionality.
For instance, does your board RREF pins has 2k resistor connection or not because I see RREF pins is floating in your pdf schematic ?
For VREF pin - the recommendation from C10 pin connection guideline doc that I shared with you is
That's why I recommend you to review the C10 pin connection guildeline doc.
If everything is done correctly on your board design connection yet your ATX PLL in toolkit design still can't lock then you need to check following
Thank you for recommending
I didn't use any voltage reference differcial IO. only 1.8V, 3.0V LVMOS and LVDS. So I will tie all VREF to GND. I didn't tie it to GND all other design I did before.
Thanks for the update on VREF pins connection but anyway this is slightly off topic and VREF shouldn't impact DsiplayPort design.
Why not you focus back to debug on the transceiver refclk pin that's likely causing Rx CDR to loose lock issue ?
I attached two picture and rx_analogreset, rx_digitalreset and rx_is_lockedtodata signal look good.
But still PC generate link failure (attached pic).
I think the failure is in DisplayPort link training sequence. I looked rx_reconfig read/write signal group and rx_link_rate_8bit appeared "14h, 0Ah, 06h. so PHY reconfiguration looks good.
Can you provide more information of DisplayPort link training sequence and aux channel access command to analyze problem ?
Any other check point do I need ?
I have one more question about rx_analog_mappings module.
There are some output to control analog circuit ( out_dc, out_ac, out_vga) but it doesn't have analog circuit.