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Cyclone 10 LP M9K Packed Mode

Patina
Beginner
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Hi, I am using Cyclone 10 LP.   

 

I need to use M9K  memory in Packed Mode because my project requires a lot of small memory blocks for small LUT (look-up table). 

 

The size of the LUTs is 8 bits x 340 words (9 bit wide).  

 

But, according to Fitter RAM Summary,  two blocks are used for each LUT, not a half of one M9K memory. 

The Fitter RAM Summary lists the attributes (parameters) as follows:

Type  : M9K

Mode  : Single Port

Clock Mode : Single Clock

Port A Depth : 340

Port A Width : 8

Port B Depth & Port B Width : "--"

Port A Input Registers : Yes

Port A Output Registers : No

Port B Input  &  Output Registers : "--"

Size 2720 

Implementation Port A Depth : 340

Implementation Port A Width : 8

Implementation Bits : 2720 

M9Ks : 2

MIF  : None

Location :  M9K_X87_Y7_NO, M9K_X55_Y20_NO (depends on LUT)

 

Please check more details from the attached files.

I appreciate it if you can tell me what is wrong or missing.

 

Thanks,

Patina 

 

 

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4 Replies
Paveetirra_Srie
Employee
219 Views

Hi Patina,


Please give me a little time to investigate this issue, I will contact you back as soon as I find a possible solution.


Regards

Pavee


Patina
Beginner
202 Views

Hi Paveetirra,

 

I appreciate your reply.

 

This is my first time to open and check the Fitter RAM Summary because I have never ran out of memory in my past projects.

For that reason, I'm afraid I don't correctly understand and interpret what the Fitter RAM Summary says.

 

The error I originally got was that my design requires 317 blocks but my FPGA (10CL080YU484) has only 305 blocks.

Please open the attached PDF file.

I need eighteen 24 bit * 340 words memory blocks and a lot more for other (image) buffers and Nios II as well.

If I use Double Port Mode, the message says "your design requires 317 blocks".

 

After changing the structure as shown in the figure from Dual Port to Single Port, the error message disappeared and reports says JUST 305 blocks are used.

It seems Fitter allocates the memory blocks in Packed Mode.

But judging from  what Fitter RAM Summary says, I am not sure if Packed Mode is successfully applied by Fitter.

Especially, why  "M9Ks" column is "2" and "Location" column is  "M9K_X87_Y7_NO, M9K_X55_Y20_NO".

Again, that is why I am wondering if  I correctly understand and interpret the summary or not.

Or, I am afraid what I am doing is incorrect.

 

Thanks for your help.

Patina

Paveetirra_Srie
Employee
138 Views

Hi Patina,


Kindly refer o below link for your query. It explains more details on block design. Chapter 1.4 Design Partitioning

https://www.intel.com/content/www/us/en/docs/programmable/683247/19-4/block-based-design-flows.html




Paveetirra_Srie
Employee
128 Views

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.


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