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PROMA
Beginner
302 Views

Cyclone 10 LP PLL output to pin assignment

I have a design with a Cyclone10 LP that needs to talk to a RGMII PHY, which expects a clock signal. 

 I use a PLL to generate a 125 MHz clock, and would now like to route that to an output pin which is PLL4_CLKOUTp.

 

The fitter returns me the following warning:

Warning (15064): PLL "PLL_Cy10LP:PLL_inst|altpll:altpll_component|PLL_Cy10LP_altpll:auto_generated|pll1" output port clk[3] feeds output pin "SC3_ETH0_TX_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

 

Do you have any idea on how to solve this warning?

 

 

 

 

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1 Reply
AnandRaj_S_Intel
Employee
80 Views

Hi Pannet,

 

If you have connected to Pll output pin to PLL4_CLKOUTp.

You can ignore the warning.

 

Regards

Anand

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