Quartus II Lite 19.1 Linux, Cyclone 10 LP dev kit. Nios 2 error. How do I update IP core ?

[JLuke3]

Error (292019): IP core Nios II Processor (6AF7_00A2) not supported in device family Cyclone 10 LP. Choose a new device family or upgrade your IP core to a newer version. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Database only tells me about 17.1 bug to be fixed in future releases.

John Luke

[Vicky1]

Hi,

Would you like to share the project file *.qar file(Project menu->Archive Project) for replication?

Regards,

Vicky

[JLuke3]

Dear Ms. Vicky, Am trying to port a Terasic DE1 (Cylone II) project to my Cyclone 10 LP dev kit to experiment with i2s drivers as part of a project to build an audio digital filter (convolved). The original source came from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53&No=83&PartNo=4 My qar file is attached. Compiles OK for Cyclone IV but not for 10 LP. Thanks for your prompt response Regards John Luke

[Vicky1]

Hi John,

Thanks for the details but There is no .*qar (Project file) attached.

Could you please attach the project file again & confirm it after posting it in community?

Thanks,

Mr. Vicky

[JLuke3]

Dear Ms. Vicky, That is strange. The mail was sent from apple mail on a MacBook pro. The attachment shows in the entry in my sent folder and in the test mail I forwarded to myself. You may be the victim of some sort of anti virus software. Try another mail reader or try reading on a mac. Should I try something old fashioned like uuencoding the file and sending it as a text file ? Will attach the file again. Regards John Luke

[JLuke3]

Dear Vicky, Maybe it is the forum that is filtering out .qar files. IP concerns ? Your email server did not like my reply either. Have copied emails. You should also be able to recreate the problem by downloading from the Terasic link https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53&No=83&PartNo=4 and changing the family and device to 10CL025YU256I7G. Here goes again. Regards John Luke

[Vicky1]

Hi John,

Here I am attaching the *.qar file for sample and there is no any concern with IPs also, I have been doing it since long time.

let me check by recreating the issue.

Regards,

Vicky

[Vicky1]

posted a file.

[JLuke3]

Interesting maybe it makes a difference if done from inside Intel ?

The attachment was definitely on the email as it was sent out.

Will try from web page reply instead of email reply..

Seems to have worked.

Regards

John Luke

[Vicky1]

Hi,

The provided design contains verilog HDL files generated from some Mega-wizards like PLL etc. also it contains the cpu_0.v which is encrypted. so Cyclone II & Cyclone IV E devices are compatible to this design & hence design compiled successfully, since this design is provided by Terasic & there is no update about other supported devices for this design. I would like to suggest try to use same devices & supporting Quartus versions recommended by Terasic.

Regards,

Vicky