Error (292019): IP core Nios II Processor (6AF7_00A2) not supported in device family Cyclone 10 LP. Choose a new device family or upgrade your IP core to a newer version. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Database only tells me about 17.1 bug to be fixed in future releases.
Thanks for the details but There is no .*qar (Project file) attached.
Could you please attach the project file again & confirm it after posting it in community?
Here I am attaching the *.qar file for sample and there is no any concern with IPs also, I have been doing it since long time.
let me check by recreating the issue.
Interesting maybe it makes a difference if done from inside Intel ?
The attachment was definitely on the email as it was sent out.
Will try from web page reply instead of email reply..
Seems to have worked.
The provided design contains verilog HDL files generated from some Mega-wizards like PLL etc. also it contains the cpu_0.v which is encrypted. so Cyclone II & Cyclone IV E devices are compatible to this design & hence design compiled successfully, since this design is provided by Terasic & there is no update about other supported devices for this design. I would like to suggest try to use same devices & supporting Quartus versions recommended by Terasic.