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Cyclone 10GX PCI express without clk_user any solution ?

manu-solystic
Novice
1,251 Views

I have a prototype design with a Cyclone 10GX

I want to use the PCI express , but the clk_user is not connected
And if i read the documentation about the PCI express with cyclone 10Gx , this clock seems to be mandatory

But on my design, it's not possible to connect the CLK_USR  (The pin is not accessible)

Does any have a suggested solution, to have a a PCI express working 
With the use of a other clock connected to the FPGA.  with an internal connection.
I have a 100Mhz LVDS clock connected to the Cyclone 10GX, and I have also a 25Mhz HCMOS clock connected to the FPGA

These clock are used in the Cyclone 10GX design

 

Thanks for any answer 

Regards

Manuel Ribeiro 

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1 Solution
manu-solystic
Novice
1,084 Views

Hi,

So I understand that the only solution is to connect a clock on the clkuser pin

So you can close this ticket

 

regards

 

 

View solution in original post

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13 Replies
wchiah
Employee
1,238 Views

Hi,


Thanks for reaching, I will close this thread as duplicate.

Moving to https://community.intel.com/t5/forums/forumtopicpage/board-id/programmable-devices/message-id/88912#M88912


Regards,

Wincent_Intel


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wchiah
Employee
1,236 Views

Hi,


Can I know which document you are referring to ?

Can you share it with me to ensure that we both in the same channel.


Regards,

Wincent_Intel


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manu-solystic
Novice
1,221 Views

Hi 

Thanks for your answer
So I am using a cyclone 10GX    FPGA   10CX085YF672E6G   on my design

And i want to test the PCI express on my design
I use the folowing Intel Example

1) - Cyclone 10 GX - PCIe Gen1 x1 Avl-ST

2) - Cyclone 10 GX - CvP Initialization Design Example

Theses design does not work on my board, 

Clk_usr   (pin AC13) is not connected on my design, and i cannot connect any signals on this pin, 

Because this pin is not accessible (no via, or pin_escape to access for this pin)

 

So I want to know

Do i need  the clk_usr    for the pci express   HIP, 
Can I use  another clock already connected on my degin

On my design I have a 25Mhz clock, and a 100Mhz Clock, 

 

I ask if there is any way to use pci express without clk_usr, by using an internal connexion clock into the FPGA
Because the pin clkusr  AC13 is not accessible

 

Attached my design, for PCI express testing    compiled with Quartus pro  22.3

 

thanks for your help ..

regards

 

regards

 

 

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FvM
Valued Contributor III
1,221 Views
Pin connection guidelines clearly state:

"This pin is used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers".
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manu-solystic
Novice
1,216 Views

So Thanks

So i saw this item, but too late,  on my board, this pin is not connected,

So i Ask here , if there is a way to route another clock to this signals

If I can check the PCI express, on my board, without this pin
We plan to reroute this board, with this clock connected,
but what i want is to check the PCI express on my prototype board

regards


 

 

 

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wchiah
Employee
1,171 Views

Hi,


Can you please try the clock call "AA6" ?

It is quite similar with AC13.


Detail please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/10cx085.pdf



Regards,

Wincent_Intel


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manu-solystic
Novice
1,154 Views

Thanks, 

But the AA6 pin if for 484 pin FBGA  Cyclone 10  GX
On my design I have a 672  Pins FBGA , and the AA6  is  the TRST signals
I do not know if it's working on a 672 pins FBGA

Regards

 

 

 

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wchiah
Employee
1,149 Views

Hi,


Thanks for your shift response.

I dont see any other option of clock user other than that.


Perhaps you can take a try and see if it is workable or not. Let me know your finding.

Looking forward to hear back from you.


Regards,

Wincent_Intel


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wchiah
Employee
1,149 Views

Hi,


Also there is an extra notes for your information in

https://www.intel.com/content/www/us/en/docs/programmable/683417/current/transceiver-pins.html


Other than those two pins, I don't see any alternative pin to perform it.

Also, Intel does not test on the function of other pins that can perform a similar function in any historical test.


Regards,

Wincent_Intel


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wchiah
Employee
1,127 Views

Hi,


We wouldn't advise turning off the CLKUSR clock. In my view the FPGA device won't be expecting this to happen.

The CYclone 10 PCG states on page 19 :


Hope this clarified,

Regards,

Wincent_Intel


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wchiah
Employee
1,104 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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manu-solystic
Novice
1,085 Views

Hi,

So I understand that the only solution is to connect a clock on the clkuser pin

So you can close this ticket

 

regards

 

 

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wchiah
Employee
1,063 Views

Hi

 

Thanks for your understanding.

With that said, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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