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Cyclone III, DDR2 HPCII and timing

Altera_Forum
Honored Contributor II
789 Views

Trying to simulate a Cyclone III/DDR2 controller @ 150MHz on the interface. Using a pair of Micron DDR2 (MT47H64M16-3) chips, along with Micron's Verilog model of same. Trying to sim the behavior with Modelsim PE and QuartusII 9.1 (and not SOPC builder). 

 

Problem is that the sim keeps bombing on an error related to T(RC), where the HPCII seems to think 8 clocks will be enough between activates, but that is just slightly less than the Micron model suggests (53.33ns vs 55ns).  

 

Now, if I was using the Avalon bus and etc, I'd have a register to tweak to fix that, but I'm not. There is no direct T(RC) setting in HPCII. Looks to me that the Altera megafunction has miscalculated this. 

 

How to tweak?
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1 Reply
Altera_Forum
Honored Contributor II
73 Views

Never mind. A wiring error on the address lines caused the intialization to mess up. Once fixed, the timing corrected.

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