Question of cyclone3 and DDR2

[Altera_Forum]

In EMI Page 203 Table 1-19 have following description: 

 each address and control pin routes from the fpga (single pin) to all memory devices must be on the same side of the fpga.     How should I explain it?   For example,i use bank1-bank4 of EP3C40F484 to interface 64bit DDR2,can i use the remaining IO ports of all bank1-bank4 as address and control pin ?   thanks!

[Altera_Forum]

I'm not exactly familiar with the cyclone device you're using, but I assume the clue is the same as with the stratix I'm currently using: 

 The requirements of the DDR pins being on "one side" of the FPGA originates from clock distribution requirements: The IP make use of the PLL located in the middle of a side to have clock skew and signal delays low as possible. It would not be helpfull to distribuite your DDR controller over the whole FPGA.   Yes, you can use the remaining IO as address etc.. Make sure the pins can support the required function, i.e. differential outputs need to be on pins that support this (e.g. DQS/DQSN).   Hope this gives some starting points...   Regards, Peter

[Altera_Forum]

--- Quote Start ---  In EMI Page 203 Table 1-19 have following description:   each address and control pin routes from the fpga (single pin) to all memory devices must be on the same side of the fpga.     How should I explain it?   For example,i use bank1-bank4 of EP3C40F484 to interface 64bit DDR2,can i use the remaining IO ports of all bank1-bank4 as address and control pin ?   thanks!  --- Quote End ---    See table 8-1 in the Cyclone III Handbook (section 8). There seems to be no way to use one DDR2 controller to handle more than 36 DQ lines in a Cyclone III. By "side" they mean one of the four sides, comprised of two I/O banks. Use the Quartus II pin planner to see what the I/O banks look like -- and there is even a finer structure to the pin placement than "side" (see "DQ groups").  You could use two separate DDR2 controllers on two different sides of the chip to handle two separate 32bit DDR2 ram chips. But they would be separate and might not stay in sync.