I have followed the following steps:
 load and synthesize the chaining DMA example that uses PCIE hard IP
 program the sof file into my Cyclone IV GX FPGA
 open virtual box and do a lspci
I'm attaching the entire project. The chaining DMA example project (which makes use of the PCIE hard IP core) can be located here:
[q1] Why can't I see my EndPoint listed when I use the lspcie command?
[q2] The pin assignments made in the project doesn't seem to line up with the pin locations and functions described in the Cyclone IV GX transceiver board pdf (except for the pcie signals: pcie_clk, tx0,rx0)
Please help me. I'm struggling with this stupid design for almost 6 months.
My overall objective is to transfer "DEADBEEF" from my host to my EP and look at it in SignalTap in my FPGA. I also need PCIe driver on my host machine. Learning this is very important for me. If you can personally walk me through all the steps I don't even mind paying for that service.....I'm just fed up at this point.
Any (I mean Any) help truly truly appreciated
As I understand it, you encounter some issue when trying to interface with CIV GX devkit using one of the design example. To ensure we are on the same page, just would like to check with you on the following:
1. Which specific devkit that you are using ie FPGA devkit or Transceiver Starter Kit?
2. Are you using any design example generated by Quartus? Mind share with me further on where we can locate the design example to see if there is any specific existing AN or user guide for it.
3. Mind further elaborate on the issue of pin assignments in the project does not line up with devkit that you mentioned n question #2?
4. Mind share with me on the specific Linux kernel that you are using? Is it come together with the design example?
Please let me know if there is any concern. Thank you.