FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6425 Discussions

Cyclone V Avalon Memory Mapped PCIe - MSI Ref Design

Honored Contributor II

Hi All - I've implement the Cyclone V AVMM PCIe core into my design with MSI (16 bits) enabled. The issue that I'm having is that I don't see any of the app_msi_.. signals toggle when I set an interrupt from my custom logic. When the software comes down to read the CRA registers to get the msi info there's nothing set. I can see the rxm_irq bits get set but it doesn't generate an msi as I thought it would.  


I was able to signal tap some of the PCIe core signals and I can see the interrupt go down a couple of levels into the blocks but it never toggles the msi that needs to be set for my software to see. I've run through my setup with our FAE and it looks like my Qsys core is correct. For a requester/completer the CRA needs to be set and it is on my design. All I'm doing is connecting my custom logic interrupt vectors to the rxm_irq which goes back into the PCIe core. I thought this would generate an msi in the status register and software would know there was an msi. Am I seeing this the wrong way? 


Is there an AVMM PCIe ref design that has the msi implemented that works? Also, The CRA slave interface is implemented but it's not too intuitive what I'm suppose to interface it with. 


Thanks in advance, 

Jesse B
0 Kudos
1 Reply
New Contributor I

hi Jesse,

I just run into similar problem as yours, but I'm using ARRIA10 device. Do you have any ref design gotten from Intel to resolve your problem, yet ?


Thanks for any advices ​

0 Kudos