Hello,I'm fairly new to using Altera tools but I've been having problems setting up MSI/X interrupts in Qsys. I thought I would include as much info as I can in the bullet points below for your info. - Using cyclone v gx FPGA with avalon-mm Hard IP for PCIe within Qsys. - Hard IP is configured as a native endpoint, currently trying to setup MSI interrupt to be sent across a PCIe lane to a host (x86 root port). - Using x1 lane, Gen1 using the 62.5 MHz app clock. - Have multiple BARs enabled as 32-bit non pre-fetchable memory (Avalon Masters). - CRA control register slave port enabled. - Connected to our Hard IP, we have 4 slave devices each with the ability to send an IRQ. These are interconnected to the Hard IP Rx_BAR0 IRQ0-IRQ15 (Currently 0 - 3). - Set the MSI to request 4 messages. Basically our software driver in the host is not able to see more than 1 MSI interrupt being triggered. We have also tried implementing MSI-X but are unable to see any interrupts being triggered. There is an option in the Hard IP called "enable multiple msi/msi-x support"? I thought that a single MSI/X is able to send data regarding several interrupts/messages? According to the documentation if the above option is enabled, I would need to implement a custom IRQ handler in Qsys. Is this necessary based on my requirements? Regards, J
I Jayan.mistry,I've got the nearly same problem as you. I connected several irq on RXmirq pcie-interrupt port and activated it in CRA registers (0x0050). And I've got only one MSI message in host side, whatever the irq is raised on RXmirq port. However, the host told me that 4 msi are available : In linux function -> pci_msi_vec_count(pdev) return 4. But pci_enable_msi_range(pdev, 1, 4) return only 1. Martoni.
--- Quote Start --- However, the host told me that 4 msi are available : In linux function -> pci_msi_vec_count(pdev) return 4. But pci_enable_msi_range(pdev, 1, 4) return only 1. --- Quote End --- Hi All. I have same problem. Does anybody know the answer? Thanks. Best regards, Andrei.
Hi Martoni,Can you please help to provide details on how to activate interrupt registers for generating MSI interrupts in CRA slave port (0x0050)? Also can you please help to provide the host software application that you are using to verify the MSI interrupts? Is this functions, pci_msi_vec_count(pdev) and pci_enable_msi_range is available in the host sw application? Iam currently using this application for the below link: http://alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_-_arria_10 Regards linus_alt
SOrry but I met same problem as yours in past, have your problme fixed ? and coudl you tell "how to activate interrupt registers for generating MSI interrupts in CRA slave port " ? thanks a lot