FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Cyclone V GX - HARD IP PCIe - Reference Clock

JD0
Beginner
391 Views

Hello, please  I want to use Cyclone V GX (5CGXFC5C6F23C7) and 2 pcs of its HARD IP PCIe.

We have on PCB routed signals to two transceivers (GXB_0 and GXB_5) and clock signal to REFCLK1, but with bad frequency (62.5 MHz), so this pin REFCLK1 can not be used as RefClk input for PCIe HARD IP. We need frequency 100 MHz or 125 MHz (dont want now change PCB desing).  My question is, if it is possible connect, to PCIe instance from QSYS design, as a clock input for PCIe RefClk another clock source such as an output from internal PLL?? Or something else?

Thank you in advance for the answer.

JD

 

 

0 Kudos
4 Replies
SengKok_L_Intel
Moderator
370 Views

Hi,


The PCIe reference clock must be come from a dedicated clock pin. It is not recommended to use the clock from the output of the PLL.


Regards -SK


JD0
Beginner
364 Views

Hi,

thank you for quick reply. So, it is not recommended or not possible to connect output from internal PLL to RefClk input of QSYS instance of HARD PCIe? 

Because I tried to compile design with 2 pcs HARD IP PCIe generated from QSYS. I connected output from internal PLL to RefCLk signal for HARD PCIe 1 and connected output from internal PLL to RefClk signal for HARD PCIe 2.

The Quartus fitter give me this errors:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 Channel PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 Channel PLL, which is within Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP altpcie_cv_hip_avmm_hwtcl.
Info (14596): Information about the failing component(s):
Info (175028): The Channel PLL name(s): BB0004P2:u0|BB0004P2_CommCore_0:commcore_0|altpcie_cv_hip_avmm_hwtcl:pcie_cv_hip_avmm_0|altpcie_cv_hip_ast_hwtcl:c5_hip_ast|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
Error (16234): No legal location could be found out of 6 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between source fractional PLL and the Channel PLL
Info (175026): Source: fractional PLL PLL:PLL_inst|PLL_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X68_Y1_N0
Error (175022): The Channel PLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 6 locations affected
Info (175029): Channel PLL containing CHANNELPLL_X0_Y13_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y17_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y21_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y25_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y29_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y33_N9
Error (175001): The Fitter cannot place 1 Channel PLL, which is within Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP altpcie_cv_hip_avmm_hwtcl.
Info (14596): Information about the failing component(s):
Info (175028): The Channel PLL name(s): BB0004P2:u0|BB0004P2_CommCore_1:commcore_1|altpcie_cv_hip_avmm_hwtcl:pcie_cv_hip_avmm_0|altpcie_cv_hip_ast_hwtcl:c5_hip_ast|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl|altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|av_xcvr_pipe_native_hip:g_pcie_xcvr.av_xcvr_pipe_native_hip|av_xcvr_native:inst_av_xcvr_native|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
Error (16234): No legal location could be found out of 6 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between source fractional PLL and the Channel PLL
Info (175026): Source: fractional PLL PLL:PLL_inst|PLL_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X68_Y1_N0
Error (175022): The Channel PLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 6 locations affected
Info (175029): Channel PLL containing CHANNELPLL_X0_Y13_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y17_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y21_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y25_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y29_N9
Info (175029): Channel PLL containing CHANNELPLL_X0_Y33_N9
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 11 errors, 8 warnings
Error: Peak virtual memory: 5554 megabytes
Error: Processing ended: Wed Oct 13 08:59:56 2021
Error: Elapsed time: 00:00:32
Error: Total CPU time (on all processors): 00:00:28
Error (293001): Quartus Prime Full Compilation was unsuccessful. 13 errors, 407 warnings

 

So possible or not possible, beacuse does not exist path from intenal PLL output to RefClk input of QSYS HARD PCIe?

 

Thank you for your reply.

Regards,

JD

SengKok_L_Intel
Moderator
323 Views

Hi,


Yes, this is unable to use the output of the PLL as the PCIe reference clock.



SengKok_L_Intel
Moderator
233 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Reply