PCIe LTSSM debug

[samhuel]

Hi FPGA designer, 

I'am currently working on a custom board. I have a c10GX105 connected in PCIe (x1) to a iMX7 SOM.

I have some trouble with PCIe connection.

I'am stuck in LTSSM state x"0F", so L0 state.

So any ideas of what could be in cause, maybe something wrong in the hardware I've duplicate the design and succesfully test it with c10gx toolkit and iMX7 development board.

BR.

[SengKok_L_Intel]

Stuck or stable at LTSSM 0xF or L0 state is expected. Which mean the PCIe link is training up to the final state. What is your expectation on LTSSM state?

Regards -SK

[samhuel]

On the iMX I don’t see something satisfaying using lspci -v command.
On my design I use 2 Bar and each are connected to onchip memory.
Lspci just tell there is a bridge connected and nothing more, don’t see the right size of bar (on chip memory). I know imx limitation (32 bits and 128M of memory max).
BR.

[SengKok_L_Intel]

Hi,

Probably you can let us know what you see from the lspci command, the actual size of onchip memory that you connected to BARs, and also your expectation, so that we can assist you further. Thanks. 

[SengKok_L_Intel]

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.