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Cyclone V PCIe Avalon-MM IP missing from Quartus Prime

Altera_Forum
Honored Contributor II
1,152 Views

This seems like a pretty simple question, but I am stumped as to why I do not see the Cyclone V PCIe Avalon-MM IP in Quartus Prime. 

 

I have tried Quartus Prime (Standard Edition) versions 17.0, 16.1 and 15.1. When I look under the Installed IP library, Interface Protocols, PCI Express, the only IP that shows up are "Cyclone V Hard IP for PCI Express" and "PHY IP Core for PCI Express (PIPE) v15.1". When I select the "Cyclone V Hard IP for PCI Express", the only interface types that are shown are Avalon-ST 64-bit and Avalon-ST 128-bit. 

 

What am I missing here? 

 

For what it's worth, I am using the Cyclone V SoC 5CSXFC6D6F31C6.
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3 Replies
Altera_Forum
Honored Contributor II
92 Views

Not sure. The MM version is certainly available and compatible with Cyclone V. It may be a mix of other parameters that are preventing it from working. For example, the MM version for Cyclone V does not support a multi-function endpoint, while the ST version does. Check your other parameter settings to see if something else is preventing you from using the MM version.

Altera_Forum
Honored Contributor II
92 Views

The PCIe hard IP core is natively Avalon-ST. To get the Avalon-MM interface a soft Avalon-ST to Avalon-MM bridge has to be added, and you can only get that if you instantiate the core in Qsys. If you don't use Qsys you only get to use the native Avalon-ST version.

Altera_Forum
Honored Contributor II
92 Views

 

--- Quote Start ---  

The PCIe hard IP core is natively Avalon-ST. To get the Avalon-MM interface a soft Avalon-ST to Avalon-MM bridge has to be added, and you can only get that if you instantiate the core in Qsys. If you don't use Qsys you only get to use the native Avalon-ST version. 

--- Quote End ---  

 

 

Got it. I was talking with a colleague yesterday about this issue and he also suggested trying to instantiate it in Qsys. I was able to do that in the latest Quartus Prime (17.0). This is my first time using Altera tools, so I am still getting used to everything. 

 

Thank you for your explanation as to why it can only be instantiated in Qsys. That makes more sense.
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