Cyclone V PCIe End Point Configuration Space register default values

[mstanislawski]

Hi

for a Cyclone V (5CGTFD9E5F35C7N) what are the default register setting for the PCIe configuration Space registers?

specifically i am looking for the Link Control 2 Register and its binary value for the Target Link speed,

Where could i verify that in the Example build from Intel/Altera for the Cyclone V DMA located at:

https://www.intel.com/content/www/us/en/design-example/714935/cyclone-v-fpga-pcie-2-0-x4-avalon-memory-mapped-dma-on-chip-and-external-memory-design-example.html

regards

Mateusz

[RongYuan]

Hi Mateusz,

In linux, you can use lspci -xxxd 1172: to see config space.

Regards,

Rong

[mstanislawski]

Hi

the goal of this effort is to figure out the actual default starting values prior to system negotiation for PCIe link training that is the value of what is programmed into the register by default from the FPGA IP Core, the Cyclone V Avalon Memory Mapped Interface for PCI Express Solutions User Guide (table 4-12) is very confusing on the matter if not conflicting with the PCI SIG definition of the register. hence i am trying to figure out if the user guide has a typo and the FPGA code has the correct value or are both set differently? 

[RongYuan]

I think the purpose of tl_cfg_ctl is to collect some important PCIe registers thus user can check them at one place. The arrangement of these registers could be somewhat confused since the offset now is not the offset in PCIe spec.

Please notice that both tl_cfg_tl_cfg_ctl and tl_cfg_tl_cfg_add are output signals. The doc says "They update every eight coreclkout_hip cycles" that means these two signals continue sending out data. Therefore you can have registers collecting them for you to check.

For example, when tl_cfg_tl_cfg_ctl=0x0040_0002 and tl_cfg_tl_cfg_add =0x2, the cfg_link_ctrl2[15:0]=0x0002 in link control 2 register means target link speed is gen2.

Regards,

Rong