FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Cyclone V Reconfigurable PLL

Altera_Forum
Honored Contributor II
1,040 Views

I am attempting to use a reconfigurable PLL in a Cyclone V. I am using two routes – ModelSim Starter as provided with Intel FPGA toolset(Ver 16.1) and a full blown version of Modelsim (10.5a). I am having issues with both routes at the moment: 

 

1. ModelSim Starter 10.5b 

 

# Loading rtl_lib.cpu_pll_0002 

# ** Fatal: Bad library format, library not compiled with Intel FPGA Edition compiler. 

# Time: 0 ps Iteration: 0 Instance: /sys_clk_gen_tb/uut/cpu_pll_inst/cpu_pll_inst File: D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Altera_IP/CPU_PLL/cpu_pll/cpu_pll_0002.v 

# FATAL ERROR while loading design 

# Error loading design 

 

This error occurs despite deleting the library and recompiling to give me a clean build. 

 

2. ModelSim 10.5a 

 

# Loading C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/altera_lnsim.altera_cyclonev_pll 

# ** Error: (vsim-3033) C:/intelFPGA/16.1/quartus/eda/sim_lib/altera_lnsim.sv(27862): Instantiation of 'cyclonev_ffpll_reconfig' failed. The design unit was not found. 

# Time: 0 ns Iteration: 0 Instance: /sys_clk_gen_tb/uut/sys_pll_inst/system_pll_inst/altera_pll_i/genblk2/genblk2/cyclonev_pll File: C:/intelFPGA/16.1/quartus/eda/sim_lib/altera_lnsim.sv 

# Searched libraries: 

# C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/altera_lnsim 

# C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/cyclonev_ver 

# D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Modules/sys_clk_gen/V1.0/Implementation/sim/modelsim/rtl_lib 

# D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Modules/sys_clk_gen/V1.0/Implementation/sim/modelsim/rtl_lib 

# Loading work.altera_pll_reconfig_core 

# Loading work.altera_std_synchronizer 

# Loading work.dyn_phase_shift 

# Loading work.generic_lcell_comb 

# Loading work.self_reset 

# Loading work.dprio_mux 

# Loading work.fpll_dprio_init 

# Error loading design 

 

I assume I am missing a library but I am not sure which one- I have manually compiled all the cyclone v libraries but I cannot see any reference to the missing design unit in any of these libraries. 

 

Anyone got any suggestions.....
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
167 Views

I met the same problem just now... I'll try 15.1 ...

Altera_Forum
Honored Contributor II
167 Views

Did you find a solution? I got stuck in the same problem :(

Reply