Cyclone V errata TLP Corruption in x2 Mode

[NGord]

I have just noticed Cyclone V errata TLP Corruption in x2 Mode.
Can you please shed some extra light on this, it was only posted last year after about 10 years!

We have been using x2 mode for years now.

What precisely are the observed symptoms when this random corruption occurs?

[ventt]

Hi @NGord,

Thanks for reaching out to the Intel Community Forum.

After checking the records, the issue was discovered in hardware. It was found when corrupted TLP packets were sent by the PCIe HIP to the application logic when the link was in Recovery mode. The x2 mode has been removed from the IP Parameter Editor starting from Quartus Prime Standard Edition v23.1.

The options are to redesign the product to not use x2 mode; instead, use a Gen 2x4 with only two lanes connected, or a Gen 1x4 with all lanes connected. These two options provide the design with the same throughput.

Thanks.

Best Regards,

VenTing_Intel

[NGord]

To clarify, if I am using Gen 1 2 lanes, I can simply change to Gen 1 4 lanes, 2 unused and I will get the same performance?

[ventt · Accepted solution]

Hi @NGord,

Yes, redesigning it to Gen 1x4 with only 2 lanes connected will provide the same throughput.

Thanks.

Best Regards,

VenTing_Intel

[NGord]

Thanks

[ventt]

Hi @NGord,

I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

VenTing_Intel

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