Cyclone V hard memory controller config for two DDR3 chips

[Altera_Forum]

Hello all, I am trying to interface with two Micron x16 DDR3 chips from a Cyclone V. 

I plan to use shared address and control signals and separate data lines to create a 32 bit interface. Is it possible to create this type of interface with just one hard memory controller? If so how do I indicate this type of design in the IP mega-wizard?  I am mainly concerned about the initialization and calibration if the controller does not know there are two chips and instead thinks it is calibrating only one.  Thanks in advance!

[Altera_Forum]

Please disregard, I found the answer in another thread. 

 Thanks