FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

Cyclone V hard memory controller config for two DDR3 chips

Altera_Forum
Honored Contributor II
‎06-25-2018 08:40 PM
1,159 Views

Hello all, I am trying to interface with two Micron x16 DDR3 chips from a Cyclone V. 

I plan to use shared address and control signals and separate data lines to create a 32 bit interface. 

Is it possible to create this type of interface with just one hard memory controller? 

If so how do I indicate this type of design in the IP mega-wizard?  

I am mainly concerned about the initialization and calibration if the controller does not know there are two chips and instead thinks it is calibrating only one. 

 

Thanks in advance!
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎06-26-2018 01:25 PM
432 Views

Please disregard, I found the answer in another thread. 

 

Thanks
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.