I'm working on a Cyclone V design that has several transceivers. I've added error counters for the rx_disperr and rx_errdetect status ports. They run on the rrefclk clock domain coming out of the transceiver.
I'm unable to ever see these error outputs set to logic one. There's no activity on these ports when disconnecting and reconnecting the SMA cable. The general status outputs appear to be working fine and the link comes up each time I plug the cable back in.
I'm using the altera_xcvr_custom_phy IP v19.1 with Quartus v20.1.1 Build 720.
Are these status outputs operational for Cyclone V?
I'm very surprised that wiggling a loose SMA connector won't cause errors. How can I force an error to prove that my error counters are operational?
As I understand it, you have some inquiries related to the rx_disperr and rx_errdetect. Based on my experience, these signals will toggle when there is an 8b10b error occurs which might be due to signal integrity problem or data error. When the cable is disconnected, the CDR may lose lock and I am not sure if the 8b10b error status signal will still work.
Can you try with the following:
1. Enable the tx_forcedisp in Custom PHY. Then in user mode, assert this signal to forcefully change the running disparity. Ideally you should see rx_disperr asserts at the RX side.
2. Create a simple one channel test design with Native PHY and repeat similar test if can replicate the observation.
Please let me know if there is any concern. Thank you.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.