FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

CycloneV ddr2 hw uniphy ip, does the four PORT is to decrease the MM IF frequency?

Honored Contributor I

Hi, I am working with the DDR2 uniphy ip, 


DDR2 IPCORE 270MHz,16bit,BL=4. 


4 PORT type=read,width=32, priority=7,5,3,1 weight=0. 


avalon MM 59MHz,BL=32. 


Four ports could read 960 data within the 64us, 960*4/64us=60MHz,this result is only Equivalent to a port,why? 



How to set the PORT Type-Width-Priority-Weight and ddr bank to work Optimaly? 



0 Kudos
0 Replies