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CycloneV ddr2 hw uniphy ip, does the four PORT is to decrease the MM IF frequency?

Altera_Forum
Honored Contributor II
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Hi, I am working with the DDR2 uniphy ip, 

 

DDR2 IPCORE 270MHz,16bit,BL=4. 

 

4 PORT type=read,width=32, priority=7,5,3,1 weight=0. 

 

avalon MM 59MHz,BL=32. 

 

Four ports could read 960 data within the 64us, 960*4/64us=60MHz,this result is only Equivalent to a port,why? 

 

 

How to set the PORT Type-Width-Priority-Weight and ddr bank to work Optimaly? 

 

 

Thanks.
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