CycloneV ddr2 hw uniphy ip, does the four PORT is to decrease the MM IF frequency?

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

CycloneV ddr2 hw uniphy ip, does the four PORT is to decrease the MM IF frequency?

997 Views

Hi,now I am working with the CycloneV DDR2 hw uniphy ip core, DDR2 270MHz,16bit,BL=4.

4 PORT Type = read,Width=32,priority =7,5,3,1,weight=0, different ddr bank.

Interface MM 59MHz,BL=32.

Four ports could read 960 data within the 64us, 960*4/64us=60MHz,this result is only Equivalent to a port，why?

How to set the PORT Type-Width-Priority-Weight and ddr bank to work Optimaly?

http://www.alteraforum.com/forum/attachment.php?attachmentid=10102&stc=1

20 KB

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.