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CycloneV ddr2 hw uniphy ip, does the four PORT is to decrease the MM IF frequency?

Honored Contributor II

Hi,now I am working with the CycloneV DDR2 hw uniphy ip core, DDR2 270MHz,16bit,BL=4. 

4 PORT Type = read,Width=32,priority =7,5,3,1,weight=0, different ddr bank. 

Interface MM 59MHz,BL=32. 


Four ports could read 960 data within the 64us, 960*4/64us=60MHz,this result is only Equivalent to a port,why? 


How to set the PORT Type-Width-Priority-Weight and ddr bank to work Optimaly? 

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