06-02-2017 01:50 PM
Hello,In the DCFIFO documentation i see that DCFIFO_MIXED_WIDTHS is supported for Arria 10 with several combination of widths of input and output ports. This is also indicated in table 12 on https://www.altera.com/documentation/eis1414462767872.html. Can I conclude that the function is not supported on other FPGA types than Arria 10 ? (I tried in on a Cyclone V with a 16 => 8 bit combination. Only 8 of the 16 bits are passed through the FIFO in Modelsim and the test on my DE0-CV shows the same result. I saw no warnings that the function is not supported in the Quartus 7.0 output.) Best Regards, Johi.
06-02-2017 02:34 PM
Hi,DCFIFO with different port widths (width ratio in a power of 2) works in Cyclone family. Maybe there is error in your code in write or read logic or FIFO parameters?
06-02-2017 07:30 PM
Hello vlrean,Thanks for the reply. Further testing learns you are right. The ALTERA documentation would have been even better if all FPGA types would have been mentioned or none at all. Best regards, John.