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Stratix V 10G MAC IP undeflow problem

Altera_Forum
Honored Contributor II
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Hi, 

 

My modules should transmit Ethernet packets at 10G to the MAC IP via Avalon ST interface. I have supplied both tx_clk and rx_clock with the 156.25MHz clocks... 

 

In the middle of every single packet, ready signal is deasserted by the MAC IP. My logic handles everything correctly (according to the Avalon ST standard), but still, in the MAC documentation is written that this event is an underflow error and all data after this ready deassertion will be dropped. This causes every single packet to fail (please see the Attachment for recorded diagrams). 

 

I don't understand why this happens, since I am sending data on every clock cycle. 

 

After ready goes back high, my logic must deasserts the valid signal for 3 clock cycles because reading from M20K needs to be restarted from previous value and M20k has 3 cycle latency between valid address and valid data. 

 

Can you help? 

 

Best regards, 

Ivan Mitic
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