FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR-2 IP data error

Honored Contributor II

Hi All,  


We are working on DDR2-IP on two different Altera cyclone III EP3C120F780C7N development kit 


1st-kit, called as A-kit  

The DDR(Micron) part number: combination of 8LD42-D9GMG and 8FB41-D90PN 


2nd-kit, called as B-kit 

The DDR(Micron) part number: combination of 8YF12-D9JLR and 8EB41-D9DPN 


The data write and read are working good with the A-kit where as there is data corruption on some addresses while working on B-kit. We used the signal tap to check DDR-2 protocol, the protocol seems to be non-violated. 


Can anyone experienced the some similar problem, please do send the response on how we can handle this case. 


Thanks and Regards, 

Vijay K
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Honored Contributor II

Timings are ok? What's the max freq of each chip? What's the controller freq?

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