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DDR HP Controller, writes changes behaviour

Altera_Forum
Honored Contributor II
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Hi, 

I upgraded a design from the native controller to the native HP controller. 

It works from 10 min to half a day, but suddenly the writes change behavior. 

 

Correct operation: 

Write goes high and stay there for several pages.  

Write_data_req goes high and stays there until a page change is performed, then it goes back on. I use this to control a fifo. So I am able of bursting data at full clock speed. (with the exception of the page changes). 

 

Suddenly the write data reqest starts to accepts burst of 8. It stays high for 8 beats, then it goes low for 5 beats, and back on. I keep write asserted the whole time. 

 

The data is clocked in using a fifo, and the result is that I have to multiple the fifo size. 

Not ideal.. 

I cannot find any changes in the phy/dll tracking using STap. 

 

Has anyone seen this behaviour before? 

I am using a 16bit DDR from micron, running at 100MHz. 

Full data rate. 

 

 

apus
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