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Valued Contributor III
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DDR SDRA IP local address

I try to use DDR SDRAM IP controller. 

I need it for 1 Gbyte DDR memory. 

after setting the block and the controller sign that we have 1 Gbyet memory we only get 26 address line, and we need 27 address line. 

did some one use the DDR controller for 1 Gbyte memoroy?
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Valued Contributor III
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What configuration are you using? For example a 1GB RAM that has a x32 off-chip interface in half-rate mode will be x128 on the local side. That will result in 26 address lines. That same memory in full-rate mode will appear as a x64 on the local side and expose 27 address lines.

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Valued Contributor III
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Thank you for the fast replay. 

I am using 128 data bus. 

and is work with address bit 0 stack to we have only 25 address bus so we dont have 26 bit address bus.
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Valued Contributor III
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Ok, for a x128 local side data path 26 bits sounds right. 

 

log2(1024*1024*1024 Bytes/16 Bytes per word) = 26 

 

I'm not sure what an address bit 0 stack is so I can't really comment further about that. If you were to ground out one of the address bits that will get you to 25 connected address lines however that will limit you to only using half the memory available on the DIMM. Others sometimes use something called a "window" bridge where you control how much address space of the memory you want to be able to access at any given time.
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Valued Contributor III
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Thank you again. 

On the first time we did try to use all the 26 address line and we saw that we trying to write and read from address 0 & 1 and we find out that the data was same, after that we r that in the ddr controller paper was the next lines: 

 

■ Full rate controllers 

The width of this bus is sized using the following equation: 

For one chip select: 

width = bank bits + row bits + column bits – 1 

For multiple chip selects: 

width = chip bits + bank bits + row bits + column bits – 1 

If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits 

wide, then the local address is 24 bits wide. To map local_address to 

bank, row and column address: 

local_address[23:22] = bank address [1:0] 

local_address[21:9] = row address [13:0] 

local_address [8:0] = col_address[9:1] 

The least significant bit (LSB) of the column address (multiples of four) on the 

memory side is ignored, because the local data width is twice that of the 

memory data bus width. 

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Valued Contributor III
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Yes that's correct, that is how the local address is mapped to the multiplexed address that is sent to the SDRAM device. 

 

You mentioned that accessing address 0 and 1 mapped to the same memory cells, were you performing burst accesses on the local side? If so are you aware of SDRAM burst wrapping? Basically if you perform a burst access that crosses a burst boundary then the address wraps around which might be why you are seeing this overlapping issue.
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Valued Contributor III
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Thank you again. 

Basically we are not working in burst mode. 

We are doing single read and write access. 

Do you any idea how we can expend the number of IP address lines? 

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Valued Contributor III
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The number of address bits are determined by this formula: 

 

log2 ([SDRAM address span * 8] / [SDRAM local data width]) 

 

For a given memory device the address span is fixed so if you wanted more or less address bits you need either wider or more narrow memory. Assuming you are mastering this memory with a 64-bit data path then you would just wire the word addresses from the memory master to the SDRAM controller. You may have the last 27th address bit floating but that just means you are not using up the entire addressable memory of your master.
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